Platforms
A PCIe Write Can Be Posted Without a Completion Packet
A conventional PCIe Memory Write carries its data in a posted request without a transaction-layer Completion response. A successful Memory Read returns data through one or more Completion with Data packets. Link acknowledgements and NVMe completion-queue entries concern different events. Before comparing supplier counts, identify the packet or record type, observation point and work represented.
The request type determines whether a Completion is expected
A transaction-layer packet, or TLP, carries a PCIe transaction. In Altera's F-Tile Avalon Streaming IP guide 25.3, RX Flow Control, dated October 8, 2026, Table 13 places Memory Write in the posted class and Memory Read in the non-posted class. The accompanying definitions distinguish requests requiring a Completion from those requiring no response.
The write's data travels forward with its request. Altera's separate L-/H-Tile DMA description explicitly describes Memory Write TLPs containing data payload. A successful read instead brings the requested data back in Completion with Data TLPs. That return path makes the read request and its returned data separate packet populations.
This article uses the conventional transaction classes documented in the cited F-Tile 25.3 page. Optional UIO and newer transaction extensions require separate interpretation. Even within Table 13, I/O Write and Configuration Write are non-posted: the word write alone does not identify the response requirement.
A link ACK has a different job
Altera's F-Tile 25.3 Data Link Layer page, also dated October 8, 2026, places ACK/NAK handling alongside packet-integrity checks and the retry buffer. It describes retransmission after a NAK or replay timeout and discarding acknowledged packets from that buffer.
These messages are data-link-layer packets, or DLLPs. A link ACK concerns receipt at that link's data-link boundary. A posted request can participate in link acknowledgement without acquiring a transaction-layer Completion response.
This prevents treating the absence of a write Completion as missing traffic, or a link ACK as proof that the application finished. The class label supplies no universal ordering, error-free delivery or durability guarantee. An ACK count needs its own definition; do not assume one ACK DLLP for each TLP.
References: [PC2]
CPU write retirement does not establish device arrival
The upstream Linux Device I/O documentation supplies a useful host-side example. It explains that posted PCI writes can be asynchronous even where accessors provide ordering properties. Its device-memory discussion says that on many platforms and buses, the CPU can retire a posted write instruction before the write reaches the target device.
A supplier's CPU-side finished label therefore needs an endpoint definition. Retirement of the instruction, arrival at the device and completion of work triggered by the write are distinct observations. An interval ending at retirement leaves the device-arrival and useful-result times unanswered. Have the platform supplier identify which event its write-time claim actually observes.
References: [PC3]
An NVMe completion entry belongs to the command layer
NVM Express's historical 2018 architecture explainer describes submission and completion queues in system DRAM and separate data structures for NVMe commands and command completions. A completion-queue entry is a record about an NVMe command. Its name does not identify a PCIe Completion TLP.
For a storage offer, ask whether completions means PCIe packets, NVMe command-result entries or an application's declared result. Those populations cannot be exchanged in a comparison merely because the report uses the same noun. A packet count alone supplies neither the number of storage commands nor their status.
The related NVMe queue article develops command organization and outstanding work. The RDMA article covers transport work-completion records and application durability. Here, the necessary distinction is the protocol object being counted.
References: [PC4]
One read request can return through several packets
Altera's P-Tile guide 25.1.1, Completion Buffer Size, dated December 15, 2025, explicitly permits a single Memory Read response to use multiple Completions. Its examples depend on the request's address, length and Read Completion Boundary, or RCB.
RCB constrains permitted split boundaries; it does not require every response packet to equal the RCB size. The guide illustrates several permitted packet combinations for the same request. Consequently, a larger Completion count can reflect a different permitted division of returned data. Count the returned bytes and identify the actual splitting conditions before interpreting the packet total.
References: [PC5]
PC-286: five requests, four Completions and nine TLPs
PC-286 is a wholly invented finite transaction population, not a capture or product result. It contains three posted Memory Write request TLPs, each carrying 64 bytes, and two Memory Read request TLPs, each requesting 128 bytes. Each read begins at a 128-byte-aligned address. Stipulate a supported 64-byte RCB and exactly two successful 64-byte Completion with Data TLPs for each read. There are no errors, retries or other transaction traffic in the example.
The request count is 3 + 2 = 5 TLPs. The three writes carry 3 x 64 = 192 payload bytes. Their stipulated posted type requires zero Completion responses; that zero is expected and supplies no evidence of loss.
The two reads request 2 x 128 = 256 bytes. Their stipulated responses contain 2 x 2 = 4 Completion TLPs, carrying 4 x 64 = 256 returned data bytes. The chosen 64-byte division is an input to the example, not a universal consequence of a 128-byte read or a 64-byte RCB.
Counting the requests and their Completion responses together gives 5 + 4 = 9 TLPs. Five, four and nine are all correct counts of different populations. The four Completion packets answer two reads; they do not imply four read requests or one missing response among five requests.
The 192 write bytes and 256 returned read bytes describe payload quantities in opposite transaction directions. This example provides no packet-overhead total, link-ACK count, elapsed interval or NVMe-command count. None of these finite totals establishes a rate or completed application work.
Compare the populations before ranking the offers
Suppose two fictional supplier summaries describe the complete PC-286 population. A reports five requests; B reports nine request-plus-Completion TLPs. Both totals reconcile with the same stipulated work. B's larger number supplies no evidence of more useful work or greater speed. If B reports four Completions instead, that figure also reconciles once its filter is identified.
An actual comparison needs the counter's documented meaning and the observation boundary. Ask which link or interface was observed, which direction was counted, whether the total includes requests, Completion TLPs or DLLPs, and how errors or replayed traffic are treated. For read returns, retain both the packet count and the data quantity. A named filter can make a useful partial report understandable; an unexplained packets label leaves the population unresolved.
Then connect the observation to the requirement. A transaction-payload rate needs a stated byte population and elapsed interval. A successful storage-command result needs command-level evidence and status. An application completion claim needs the application's declared finish. Each additional conclusion needs the observation that actually supports it.
If one offer counts read-response packets and the other counts NVMe command results, request comparable evidence before ranking them. For a PCIe capacity question, the related generation-and-width article explains the separate connection-rate calculation. Neither packet counts nor a generation label alone resolves delivered application performance.
Carry the selected system into the installation inquiry
Once the customer and equipment supplier have selected the complete system, Leviathan's rack-and-stack service is relevant to agreed equipment mounting, physical IT cabling, labels and installation records. Use the related service and project-inquiry links with a nonconfidential equipment summary, appointed supplier, released rack and external connection plans, site constraints and required handoff.
Keep protocol interpretation, device and driver configuration, and workload acceptance with their appointed technical owners. The inquiry defines the separate physical installation package and availability. This article provides education for reading supplier claims, with no device-operation procedure or authorization to perform work.
References: [L1]
Primary sources
- [PC1] Altera F-Tile Avalon Streaming IP for PCI Express User Guide 25.3: RX Flow Control, October 8, 2026Checked 2026-10-20. Definitions and Table 13 establish conventional request classes. Optional UIO and newer transaction extensions need separate evidence.
- [PC2] Altera F-Tile Avalon Streaming IP for PCI Express User Guide 25.3: Data Link Layer, October 8, 2026Checked 2026-10-20. ACK/NAK, integrity and retry-buffer behavior explain the link boundary. No fixed ACK-to-TLP count is assumed.
- [PC3] Linux kernel documentation: Bus-Independent Device AccessesChecked 2026-10-20. Unversioned upstream documentation read October 20, 2026. Posted MMIO semantics explain a timing boundary; they do not establish a particular server's write latency.
- [PC4] NVM Express: Base NVM Express – Part One, historical 2018 architecture explainerChecked 2026-10-20. Queue and command-completion structures distinguish the NVMe command layer. Historical product-support ranges are not used.
- [PC5] Altera P-Tile Avalon Streaming FPGA IP for PCI Express User Guide 25.1.1: Completion Buffer Size, December 15, 2025Checked 2026-10-20. Single-read multiple-Completion prose and boundary-dependent examples support the packet distinction. PC-286's exact split is stipulated; no buffer sizing or device configuration is prescribed.
- [PC6] Altera L-/H-Tile Avalon Memory-mapped IP for PCI Express User Guide 23.4: internal-descriptor-controller DMA interfaces, September 23, 2026Checked 2026-10-20. The PCIe Write DMA Data Master description explicitly identifies Memory Write TLPs carrying data payload. Used only to corroborate payload direction, without transferring implementation settings or capabilities.
- [L1] Leviathan Systems: Rack-and-Stack and Colocation InstallationChecked 2026-10-20. Existing physical service scope covers agreed mounting, IT cabling, labels and installation records. Project scope and availability require the installation inquiry.