Planning
SSD Capacity Does Not Tell You Its NAND Parallel Organization
Equal SSD capacity does not establish equal NAND organization. Vertical cell layers, planes within a die, physical dies and shared NAND-interface channels describe different resources. Their counts reveal opportunities and constraints for parallel work; a performance claim still needs eligible operations, controller scheduling and evidence for the required workload. The fictional example below holds raw capacity constant while changing the total plane count from 24 to 12.
232 layers and six planes count different structures
In 3D NAND, vertical cell layers increase storage density within silicon. A plane is a partition of the NAND array within a die. Micron's historical 232-layer explanation describes adding vertical cell-array layers separately from partitioning the device into six planes to support more parallel activity. A layer count is therefore not a plane count.
Micron's July 26, 2022 release identifies its then-new 232-layer NAND as six-plane TLC with independent read capability in each plane. That is a named historical architecture example, rather than a current market ranking or a feature assigned here to an unspecified SSD. The independent-read statement also does not establish unrestricted overlap of every operation type.
Separate a physical die, its package and its data path
Here, die means a physical piece of NAND silicon, package means the component enclosing one or more dies, and SSD means the complete drive. These terms prevent an ambiguous chip count from doing several jobs. KIOXIA's BiCS FLASH technology page explicitly describes assembling multiple NAND dies into one package. Counting visible packages cannot establish the number of dies inside them.
A NAND channel describes an interface path between the flash controller and connected NAND. Multiple media resources can share that path. Micron's calculator separately describes host NAND data-bus channels and package channels sharing a host channel. These are internal NAND connections, distinct from the SSD's host-facing PCIe interface.
The useful architectural question is how the dies and their planes connect to the available paths. Adding another die or another plane does not, by itself, add another independent channel.
The same 1,024 Gibit can contain 24 planes or 12
Consider two invented NAND assemblies, A and B. A contains four dies, each with exactly 256 Gibit of raw capacity and six planes. B contains two dies, each with exactly 512 Gibit of raw capacity and six planes. Gibit means gibibit: 2^30 bits. These inputs describe no real product, and no host-visible capacity is stipulated.
A's raw total is 4 x 256 = 1,024 Gibit. B's is 2 x 512 = 1,024 Gibit. Equal totals have been reached through different combinations of die count and capacity per die.
A contains 4 x 6 = 24 planes. B contains 2 x 6 = 12 planes. Both have six planes per die, so quoting only that per-die figure would hide the difference in the assemblies. Quoting only total raw capacity would hide both the die-count difference and the plane-count difference.
The 24-to-12 ratio is a count ratio. It supplies no throughput, latency or IOPS ratio. The assumptions provide neither channel connections nor operation timings, eligible combinations of operations, placement of the requested data or controller behavior. There is no basis for saying A finishes a workload twice as quickly.
This example also shows why a denser die can change an equal-capacity comparison without proving a performance regression. B requires fewer dies to reach the same raw total. Whether its complete implementation serves the buyer's workload better or worse remains an evidence question.
References: [U1]
A plane count does not make every request combination eligible
Parallel execution requires compatible work. Agrawal and colleagues' 2008 SSD-design paper gives a concrete historical example: its examined NAND component permits particular pairs of planes for two-plane commands, while excluding other pairings. Its rule is not a specification for present-day NAND; it demonstrates why a partition count alone cannot describe permissible combinations.
For an offered device, ask which operation types and address combinations the documented capability covers. Independent reads, multi-plane programming and overlap between different operation types are separate claims. A feature stated for one must not silently become permission for all three.
A controller also needs suitable work ready to issue. A later request that depends on an earlier result cannot become independent merely because another plane exists.
References: [S1]
Resource inventory and concurrent use need separate descriptions
Micron's undated NAND system-power calculator, checked October 20, 2026, asks separately for channel count, resources per channel under its LUNs/die label, and resources busy at the same time with specified operations. It also separates array-operation timing from interface speed. Those inputs distinguish physical organization from activity; the tool estimates power and energy, rather than certifying SSD performance.
Retain the calculator's terminology without treating LUN and physical die as universal synonyms. In the 2017 LightNVM paper's open-channel model, exposed parallel units, also called LUNs, may cover more than one physical die. The authors then explicitly assume one die per unit for their analysis. That model illustrates why the mapping must be stated; it does not describe an ordinary SSD's host interface.
For a supplier's count, establish what is being counted and at which interface. Then distinguish how many resources exist from how many are simultaneously doing the relevant work. Neither count can substitute for the other.
Use topology to examine a claim, then evidence to judge the workload
Imagine two capacity-matched offers. A supplies capacity and layer count. B additionally documents die capacity, die count, planes per die and the channel arrangement for its offered configuration. B makes the topology claim assessable. Those additional details still do not make B the faster choice; A's missing detail does not prove an inferior implementation.
Start with the actual requirement: for example, a recurring read stage with a stated request size, access distribution, concurrency and response target. Ask how the claimed organization helps that stage, then examine applicable throughput and latency evidence. Keep the exact capacity variant, firmware and host configuration attached to that evidence. A result for a larger-capacity member of a product family does not automatically answer for the smaller offered variant.
If the supplier attributes an observed advantage specifically to more planes, ask what separates that effect from different channels, NAND timing, scheduling or workload conditions. A whole-drive comparison can demonstrate a result under its stated conditions without isolating the cause.
The related performance guide develops IOPS, throughput and latency comparisons. The garbage-collection and SLC-cache articles address prior-write state and changing write-service behavior. Those questions remain relevant when assessing a result, but neither replaces the topology evidence examined here.
Bring the selected equipment into the installation discussion
Once the storage and platform owners select the equipment, Leviathan's rack-and-stack service can address agreed equipment mounting, IT cabling, labels and physical installation records. Use the related service and project-inquiry links with a nonconfidential equipment summary, released rack and connection plans, site constraints and required handoff.
Identify the equipment supplier and the owners of storage configuration and workload acceptance. That connects the selected system to a defined physical work package while keeping its performance decision with the appointed technical owners.
References: [L1]
Primary sources
- [NP1] Micron Ships World's First 232-Layer NAND, Extends Technology Leadership, July 26, 2022Checked 2026-10-20. Historical release identifies six-plane TLC and independent per-plane reads. The example applies to that announced NAND generation; its market-leadership claims are not current rankings.
- [NP2] Micron: First to market, second to none: The world's first 232-layer NANDChecked 2026-10-20. Historical explanation discusses manufacturing ramp through the end of 2022. Its vertical-layer density and per-die plane-partition discussion supports the structural distinction.
- [NP3] Micron: NAND system power calculatorChecked 2026-10-20. Undated input descriptions distinguish channels, connected resources, concurrent busy resources, array timing and interface speed. They support reading architecture and activity separately, without supplying a drive-performance result.
- [K1] KIOXIA: Innovative Technologies That Pave Ways to Higher CapacityChecked 2026-10-20. The back-end assembly discussion explicitly distinguishes multiple physical dies from their enclosing package. Its product-capacity examples are not assigned to the fictional assemblies.
- [S1] Agrawal et al.: Design Tradeoffs for SSD Performance, USENIX 2008Checked 2026-10-20. Sections 2 and 2.2 explain shared data paths and restricted plane combinations in a historical component. Its timings and allowed pairings are not current product specifications.
- [S2] Bjorling et al.: LightNVM: The Linux Open-Channel SSD Subsystem, FAST 2017Checked 2026-10-20. Section 3.1 distinguishes exposed parallel units from physical dies in its open-channel model, before assuming one die per unit. This is a bounded terminology example.
- [U1] NIST: Prefixes for binary multiplesChecked 2026-10-20. The gibi prefix denotes 2^30. Die capacities and plane counts in the arithmetic example are original hypothetical inputs.
- [L1] Leviathan Systems: Rack-and-Stack / ColocationChecked 2026-10-20. The service describes agreed equipment mounting, IT cabling, labels and physical installation records. Its inquiry is for discussing project scope and availability.