---
title: "A Smaller Process-Node Number Is Not a Measured Chip Dimension"
description: "Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20."
canonical: "https://www.leviathansystems.co/articles/semiconductor-process-node-labels-versus-physical-dimensions"
last-updated: "2026-10-20"
---

# A Smaller Process-Node Number Is Not a Measured Chip Dimension

Leviathan Systems — Technical content
Published 2026-10-20; updated 2026-10-20.

A modern process node identifies a semiconductor manufacturing technology. Its numeric label is not a measured gate length or a universal ruler for comparing foundries. Identify the exact process and the die it describes, then assess separately defined dimensions, density and power/performance/area evidence. A smaller node number alone cannot rank accelerator speed, energy use or value.

## A node identifies a manufacturing technology

A process node combines choices about transistor structures, their interconnections and the manufacturing technology used to realize them. Intel's March 9, 2026 explanation describes this physical architecture and the process design kit, or PDK: the specifications, rules and tools used to design for that particular process.

That makes the node useful technical context. It identifies the technology a design must work within, rather than specifying the processor's entire design. Intel groups process evaluation around power, performance and area, abbreviated PPA. Those are related objectives with tradeoffs, rather than three quantities encoded by one number.

For a buyer, the distinction is practical: knowing the manufacturing technology does not tell you how the offered accelerator allocates its circuitry or performs the intended work.

References: [PN1](https://www.intel.com/content/www/us/en/newsroom/tech101/explaining-common-chip-terms.html)

## Do not square a ratio between node names

Intel's July 26, 2021 naming fact sheet is explicit: its node numbers identify neither an actual physical feature dimension nor a proportional improvement in power, performance or area. This historical statement concerns the naming convention, not the present status of that document's roadmap.

Consider two wholly fictional names, Process 10 and Process 5. Dividing their labels gives two; squaring that ratio gives four. Neither operation establishes four times the transistor density. An area-scaling calculation would need actual comparable lengths, a justified scaling relationship in both directions and assumptions about what structures occupy the area. The names supply none of those inputs.

A decreasing number can mark a vendor's process progression without providing a calibrated cross-vendor scale. Matching numbers likewise do not establish matching gate lengths, density or performance. Keep the foundry and full process designation attached to the claim.

References: [NM1](https://download.intel.com/newsroom/2021/client-computing/accelerating-process-innovation.pdf), [PN2](https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html)

## A physical dimension needs a defined feature

A length measurement must identify what was measured. Gate length and an interconnect's line width concern different features; pitch includes a feature and its spacing to the next repeated feature. A measured length, a pitch and an area per transistor therefore cannot be substituted for one another.

ASML describes lithographic resolution with CD = k1 × λ / NA. Here CD is critical dimension, the smallest possible feature size in that optical context; λ is the light wavelength, NA is the optics' numerical aperture, and k1 represents process-dependent factors. The relationship explains why wavelength, optics and process factors matter together.

This is a lithographic-resolution relationship, not a complete transistor or fabrication model. It does not turn a process name into a finished gate measurement or predict a GPU's features. A real dimensional comparison still needs the identified feature, layer, measurement definition and applicable conditions.

References: [PN3](https://www.asml.com/en/technology/lithography-principles/rayleigh-criterion), [DN1](https://download.intel.com/newsroom/2021/archive/2017-03-28-editorials-lets-clear-up-node-naming-mess.pdf)

## Two dies can have the same average without equivalent processes

Suppose two fictional single-die descriptions use the same stipulated transistor-counting rule and the complete die area as the denominator. Die A contains 10 billion counted transistors across 100 mm²; Die B contains 12 billion across 120 mm². These are invented inputs, with no mapping to a product or process.

For A, 10,000 million / 100 mm² = 100 million counted transistors/mm². For B, 12,000 million / 120 mm² gives the same 100 million/mm². B has more counted transistors and proportionally more die area. The calculated averages are equal.

That equality does not establish identical logic-cell density, SRAM content or performance targets. A whole-die average combines whatever circuitry the design contains. In his March 28, 2017 Intel editorial, Mark Bohr explains why cache sizes and performance choices affect that average, discusses a metric based on defined standard logic cells, and calls for SRAM cell size to be reported separately.

The purchasing inference is to retain the metric's population. A library claim concerns specified logic building blocks; a whole-die average concerns the complete counted design. Comparing them requires more than matching the unit. The fictional equality proves neither node equivalence nor equal workload speed, energy use or cost.

References: [DN1](https://download.intel.com/newsroom/2021/archive/2017-03-28-editorials-lets-clear-up-node-naming-mess.pdf)

## Read the population and conditions behind a PPA claim

A process comparison needs to say which circuits or library it evaluates, which process is the baseline and what is held constant. An improvement for one comparison population cannot silently become an improvement for every circuit in a finished accelerator.

Intel support article 000097598, last reviewed February 14, 2025, provides a useful scope example. Its approximately twofold logic-area scaling claim for Intel 4 versus Intel 7 explicitly concerns the high-performance logic library. It also gives a separate transistor performance-per-watt comparison at the same power. Preserve those objects and conditions: neither statement is a whole-server measurement or a ranking against another foundry's similarly numbered process.

Iso-power means comparing the stated performance measure while holding power constant at the defined boundary. Iso-performance means comparing power while holding that performance measure constant. Intel's Foundry process overview uses both formulations and identifies baselines and supporting footnotes. They answer different questions about the comparison; they do not promise the largest speed increase and lowest power simultaneously at one operating point.

For an actual claim, ask whether the evidence covers transistors, test circuits, a library, a chip or a complete system. Retain how performance is defined and the relevant operating conditions. A transistor-level iso-power improvement supplies no measured energy-per-inference result for the offered server.

References: [PN2](https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html), [PP1](https://www.intel.com/content/www/us/en/foundry/process.html)

## Assign each process claim to the die it describes

A multi-die accelerator can contain components made with different process technologies. TSMC's SoIC description explicitly supports integration of dies with different functions, sizes and wafer-node technologies. A process label attached to a compute die consequently does not characterize every I/O or memory die in its package.

Identify the die before using a published transistor count or area. Combining counts from several dies and dividing by a package footprint changes the population and denominator; it cannot be substituted for a single-die density calculation. The chiplet and packaging guide linked below explains those physical boundaries. Keep its die-to-package distinction when reading a node claim.

References: [PK1](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm)

## Use node information to qualify the comparison

If an offer gives only a smaller node label, its relative geometry, density, workload speed and energy use remain unresolved. Ask for the exact process, the constituent die it describes and the source of any claimed improvement. A useful comparison preserves the metric, baseline, population and conditions instead of filling missing fields from the number.

Then move to evidence for the outcome you need. The linked GPU benchmark guide covers application and complete-system comparisons. The arithmetic-intensity guide explains why memory traffic and compute capability can impose different limits. Neither mechanism can be replaced by a manufacturing label.

Once equipment is selected, Leviathan's rack-and-stack service addresses agreed equipment mounting, IT cabling, labels and physical installation records. Use the related project inquiry to share a nonconfidential equipment list, site, released rack and connection plans, target window and requested handoff. That discussion concerns the selected physical system; semiconductor design and application-performance evaluation require their respective owners.

References: [L1](https://www.leviathansystems.co/services/rack-and-stack)

## Primary sources

- [PN1 — Intel: Explaining Common Chip Terms](https://www.intel.com/content/www/us/en/newsroom/tech101/explaining-common-chip-terms.html). Checked 2026-10-20. March 9, 2026 explanation of process architecture, PDKs and PPA. Useful for definitions; no manufacturing yield or product-performance result is adopted.
- [PN2 — Intel: Intel 4 Versus Intel 7 and Intel Process Technology Naming](https://www.intel.com/content/www/us/en/support/articles/000097598/processors.html). Checked 2026-10-20. Article 000097598, last reviewed February 14, 2025. Library and transistor comparisons retain Intel's stated baseline and conditions, without a cross-vendor ranking.
- [PN3 — ASML: The Rayleigh Criterion](https://www.asml.com/en/technology/lithography-principles/rayleigh-criterion). Checked 2026-10-20. Defines CD, wavelength, numerical aperture and the process factor in lithographic resolution. The equation does not specify finished transistor geometry.
- [NM1 — Intel: Accelerating Process Innovation, naming explanation](https://download.intel.com/newsroom/2021/client-computing/accelerating-process-innovation.pdf). Checked 2026-10-20. July 26, 2021 fact sheet, page 3 and footnote 2. Historical naming explanation only; its roadmap dates and projected gains are not current product evidence.
- [DN1 — Mark Bohr, Intel: Let's Clear Up the Node Naming Mess](https://download.intel.com/newsroom/2021/archive/2017-03-28-editorials-lets-clear-up-node-naming-mess.pdf). Checked 2026-10-20. March 28, 2017 editorial distinguishes dimensional proxies, logic-cell metrics, whole-chip averages and SRAM. Its metric proposal is not represented as a universal standard.
- [PP1 — Intel Foundry: Manufacturing Process Technologies](https://www.intel.com/content/www/us/en/foundry/process.html). Checked 2026-10-20. The overview and supporting footnotes illustrate iso-power and iso-performance comparison framing. No advertised percentage, availability or cross-vendor advantage is adopted.
- [PK1 — TSMC: SoIC Heterogeneous Integration](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm). Checked 2026-10-20. Supports integration of dies with differing functions, sizes and process technologies. It supplies no process assignment for a named accelerator here.
- [L1 — Leviathan Systems: Rack-and-Stack and Colocation Installation](https://www.leviathansystems.co/services/rack-and-stack). Checked 2026-10-20. Published physical installation scope and project inputs support the equipment handoff described here.

## Related Leviathan resources

- [Chiplets and packaging: identify the constituent dies](/articles/gpu-chiplets-2-5d-3d-packaging-system-boundaries)
- [Compare GPU workload benchmark evidence](/articles/which-gpu-is-fastest-workload-benchmarks)
- [Understand arithmetic intensity, memory bandwidth and compute limits](/articles/gpu-memory-bandwidth-arithmetic-intensity-roofline)
- [Review rack-and-stack installation scope](/services/rack-and-stack)
- [Discuss installation of the selected equipment](/contact?service=rack-and-stack&from=%2Farticles%2Fsemiconductor-process-node-labels-versus-physical-dimensions)

## Plan installation of the selected physical system

Share the equipment, site, available rack and cable plans, target window and required handoff to discuss physical installation scope and availability.

[Discuss the scope](/contact?service=rack-and-stack&from=/articles/semiconductor-process-node-labels-versus-physical-dimensions)