--- title: "PCIe Bifurcation, Switch or Retimer: What Does the Expansion Hardware Change?" description: "Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20." canonical: "https://www.leviathansystems.co/articles/pcie-bifurcation-switch-retimer-expansion-roles" last-updated: "2026-10-20" --- # PCIe Bifurcation, Switch or Retimer: What Does the Expansion Hardware Change? Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20. PCIe bifurcation divides an available lane population into separate links. A PCIe switch connects devices through a hierarchy of ports, with host-facing traffic sharing the applicable upstream link. A retimer recovers and regenerates signals along a link. An expansion product can combine these functions, so compare the actual lane allocation, port relationships and signal-conditioning role before treating two risers or expansion devices as equivalent. ## Read lanes, links and ports as different counts An x8 link has eight lanes; it is not eight independent device connections. A lane has transmit and receive paths. Counting both directions does not turn an x8 link into x16. Upstream and downstream identify positions toward the host and toward attached devices, respectively; those labels do not make the links one-way. Keep the PCIe generation alongside each link width. Width describes the lane count, while the generation identifies the signaling context. Neither field alone states application throughput. The comparisons below concern attachment structure, with no conversion into application GB/s. References: [T4](https://www.ti.com/lit/pdf/scda012), [P1](https://pcisig.com/section-753-endpoint-sends-memory-request-upstream-switch-how-will-switch-determine-if-it-needs) ## Bifurcation organizes existing lanes into separate links Bifurcation assigns groups of existing lanes to separate links. TI's August 2022 overview illustrates x8x8 as two eight-lane endpoint links with different link numbers. The host lane population is divided rather than multiplied. Each endpoint has its own link from that allocation. Additional device positions on a riser do not establish that the host supplies the required division. Have the supplier identify support for the exact host and expansion arrangement. References: [T1](https://www.ti.com/lit/an/snla415/snla415.pdf) ## A switch adds a packet-routing relationship through ports A PCIe switch has ports connecting distinct links. It routes PCIe packets between those ports, rather than merely assigning a separate group of host lanes to each endpoint. PCI-SIG's PCI Express 3.0 routing FAQ explains how a switch directs a memory request according to its destination. Broadcom's July 17, 2019 PEX88000 brief describes a standard fan-out mode and host-to-I/O expansion in servers and storage systems. That is the bounded function used here: an upstream connection toward the host and downstream connections toward devices. Where several devices' traffic must traverse one host uplink, those flows share that uplink. Wider or more numerous downstream links do not widen it. This observation concerns traffic crossing the specified uplink; it does not assume that every transfer in every switch architecture follows that path. References: [P1](https://pcisig.com/section-753-endpoint-sends-memory-request-upstream-switch-how-will-switch-determine-if-it-needs), [B1](https://docs.broadcom.com/doc/BC-0484EN) ## A retimer changes the signal path along a link A retimer receives a signal, recovers its clock and data, and regenerates the transmitted signal. TI's December 2021 SNLA401 brief describes clock-and-data recovery as part of this signal-conditioning function. This is different work from routing packets among endpoint-facing ports. TI's link-training overview describes separate initialization on the host-to-retimer and retimer-to-endpoint portions. Those electrical segments do not amount to two independent endpoint attachments. A retimer on an eight-lane link does not, through retiming alone, turn that path into two eight-lane device links. The purchase therefore addresses signal conditioning for an identified path. A retimer label supplies no additional endpoint count or wider host connection. References: [T3](https://www.ti.com/document-viewer/lit/html/snla401), [T1](https://www.ti.com/lit/an/snla415/snla415.pdf) ## The same expansion product can combine functions TI identifies the DS160PT801 as an eight-lane PCIe 4.0 retimer and explicitly supports bifurcating those eight lanes into two x4 links. Retiming and bifurcation are therefore compatible descriptions of that component's capabilities. The two four-lane links still account for eight lanes. This example is a component reference, not complete-server qualification. It also shows why active riser is an incomplete comparison label. Ask what the named assembly actually contains and how it connects: which lanes form which links, whether a packet switch sits between host and endpoints, and which paths include retiming. Packaging several functions together does not make their effects interchangeable. References: [T2](https://www.ti.com/product/DS160PT801) ## Compare two endpoint links with different host connections Consider two fictional diagrams, A and B, each connecting endpoints E1 and E2. Assume PCIe 4.0 throughout and that every illustrated link operates at its stipulated width. All counts below are lane counts. These invented diagrams explain attachment structure; they represent no actual card, compatible server layout or measured result. A starts with 16 available host lanes organized as two separate x8 links. One goes to E1 and the other to E2, with no PCIe switch in the stipulated paths. Eight plus eight accounts for the original 16 host lanes. Bifurcation has changed the number of links supplied by that allocation. B starts with one x8 host link to a PCIe switch. The switch has two downstream x8 links, one to each endpoint. B therefore has 16 downstream lanes across two links, but only eight lanes in its host uplink. Adding the downstream widths cannot establish a 16-lane host connection. Now suppose both endpoints need to send data to the host at the same time. In B, both flows traverse the same x8 uplink. The diagram supplies no equal bandwidth allocation or application transfer rate. A has two separate host links, but its drawing likewise supplies no evidence about other host limitations or workload completion time. The comparison identifies a shared link, not a benchmark winner. For a further fictional variant, draw a retimer within A's E1 path. That path now includes the signal-recovery stage and separate electrical segments. It still accounts for the same eight host lanes and the same E1 attachment. No third endpoint appears merely because a retimer is present. Both original diagrams show two x8 endpoint connections. They buy different host attachment structures. A's lane division and B's switch fan-out cannot be treated as equivalent solely because the endpoint-side widths match. ## Choose the expansion result the offer needs to supply Start with the constraint the purchase is intended to change. Using an available host lane population for several separate links is a bifurcation question. Connecting several devices behind a host link is a switch fan-out question. Providing signal recovery within an identified link is a retiming question. A complete product may answer more than one. A shared uplink can be a deliberate tradeoff when the requirement is to attach more devices within the available host connection. Its existence does not make the expansion useless. Conversely, buying more downstream device connections does not satisfy a requirement for additional host-facing lanes. For simultaneous host transfers, the shared upstream path deserves explicit evaluation by the responsible platform and workload team. Have the OEM or system supplier establish the exact supported server, controller and expansion assembly. The linked GPU upgrade-kit article covers the separate purchase of a supported internal conversion. If the intended result includes GPU-to-NIC direct transfers, continue with the existing GPUDirect RDMA topology article: identifying a switch or retimer does not establish that application path. This is an educational comparison of component functions. Internal hardware changes, settings, electrical-channel design and operating verification require their own appointed technical scope; no installation procedure or work approval is supplied here. ## Scope physical installation around the selected complete system Once the supplier and customer have selected the complete system, Leviathan's rack-and-stack service provides a relevant route for discussing agreed equipment mounting, physical IT cabling, labels and installation records. The service and project inquiry are linked below. Bring a nonconfidential equipment summary, the appointed equipment supplier, approved rack and external connection plans, site requirements and requested window. Keep the internal expansion decision with the responsible platform team. The physical installation discussion can then concern the actual equipment package and the handoff its receiving team needs. References: [L1](https://www.leviathansystems.co/services/rack-and-stack) ## Primary sources - [T1 — Texas Instruments: PCIe Link Training Overview, SNLA415, August 2022](https://www.ti.com/lit/an/snla415/snla415.pdf). Checked 2026-10-20. Explains x8x8 link identities and the separate initialization of retimer electrical segments. - [B1 — Broadcom: PEX88000 Series Managed PCIe 4.0 Switches, BC-0484EN, July 17, 2019](https://docs.broadcom.com/doc/BC-0484EN). Checked 2026-10-20. Base-mode fan-out and host-to-I/O connectivity illustrate the switching role, without adopting advanced fabric features or performance claims. - [T2 — Texas Instruments: DS160PT801 product information](https://www.ti.com/product/DS160PT801). Checked 2026-10-20. Named eight-lane PCIe 4.0 retimer with two-x4 bifurcation support illustrates functions coexisting within a component. - [T3 — Texas Instruments: SNLA401 Application Brief, December 2021](https://www.ti.com/document-viewer/lit/html/snla401). Checked 2026-10-20. Clock-and-data recovery and signal regeneration explain the retiming mechanism; device-selection thresholds and tuning guidance are outside this comparison. - [T4 — Texas Instruments: Differential Passive Signal Switch on Computing, SCDA012A, revised July 2009](https://www.ti.com/lit/pdf/scda012). Checked 2026-10-20. Section 3.6 supplies the basic transmit/receive lane distinction. Its historical rates, topology generalizations and signal-multiplexer designs are not applied. - [P1 — PCI-SIG: PCI Express 3.0 FAQ on routing a Memory Request through a switch](https://pcisig.com/section-753-endpoint-sends-memory-request-upstream-switch-how-will-switch-determine-if-it-needs). Checked 2026-10-20. The port-routing explanation supports the packet-switch distinction. It establishes no peer-transfer support or isolation for a proposed system. - [L1 — Leviathan Systems: Rack-and-stack and colocation installation](https://www.leviathansystems.co/services/rack-and-stack). Checked 2026-10-20. Defines agreed equipment mounting, IT cabling, labels and physical installation records for the selected system. ## Related Leviathan resources - [GPU-to-NIC topology and the separate GPUDirect RDMA question](/articles/gpu-server-pcie-topology-gpudirect-rdma) - [Configured GPU server or a supported later conversion](/articles/gpu-server-factory-configuration-versus-gpu-upgrade-kit) - [LPO and retimed optics at the external network interface](/articles/gpu-network-lpo-versus-retimed-optics) - [Rack-and-stack installation for the selected system](/services/rack-and-stack) - [Discuss the selected system's physical installation](/contact?service=rack-and-stack&from=%2Farticles%2Fpcie-bifurcation-switch-retimer-expansion-roles) ## Discuss installation of the selected complete system Share the equipment summary, appointed supplier, approved rack and external connection plans, site requirements and target window so we can discuss the physical installation scope and availability. [Discuss the scope](/contact?service=rack-and-stack&from=/articles/pcie-bifurcation-switch-retimer-expansion-roles)