--- title: "NVMe Queues Organize Commands, Not NAND Channels" description: "Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20." canonical: "https://www.leviathansystems.co/articles/nvme-submission-completion-queues-versus-media-parallelism" last-updated: "2026-10-20" --- # NVMe Queues Organize Commands, Not NAND Channels Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20. Read an NVMe queue figure as a resource for organizing commands between host software and a controller. Establish the supported limit, actual allocation and workload using those resources. Neither queue count nor outstanding commands establishes a physical drive count, NAND-channel count, stored capacity or performance multiplier. ## Trace the command, its completion status and its data separately Host software places command entries in an I/O Submission Queue, or SQ. The controller takes work from that queue and posts completed-command status to the associated Completion Queue, or CQ. In the PCIe memory-based model, these queues occupy host-addressable memory. The read or write payload uses the command's specified data buffers; the CQ is not the buffer that holds the requested dataset. This separates the work description, completion report and transferred bytes. A queue identifier names a command-handling resource. It does not identify an SSD or a physical NAND channel inside one. Several SQs can share a CQ in the PCIe memory-based model. The cited Base 2.2 message-based model instead uses one-to-one associations. A supplier's queue diagram needs its transport identified. References: [N1](https://nvmexpress.org/wp-content/uploads/NVM-Express-Base-Specification-Revision-2.2-2025.03.11-Ratified-1.pdf), [P1](https://nvmexpress.org/wp-content/uploads/NVM-Express-PCI-Express-Transport-Specification-Revision-1.2-2025.03.11-Ratified-1.pdf) ## Separate supported resources, actual allocation and active use Supported is the identified controller's capability ceiling; allocated is what the host actually receives. Created queues must fit that allocation and the supported attributes. Ask for SQ and CQ counts separately. Active use adds an observation: which created queues carried work during the stated instant or interval? Here, active means observed use, not a universal device status field. Available resources can remain unused. Configured entries describe each queue's ring size. The cited pointer model leaves one slot unavailable for use. Ring occupancy also differs from unfinished work: consuming an SQ entry and completing its command are separate events. For ordinary operation without an intervening reset, cancellation or other retirement event, outstanding commands are submitted commands for which the host has not received completion. A submitted-command total over an interval can include work already completed. Completions observed over an interval count another population; their status still matters when interpreting successful work. References: [N1](https://nvmexpress.org/wp-content/uploads/NVM-Express-Base-Specification-Revision-2.2-2025.03.11-Ratified-1.pdf), [P1](https://nvmexpress.org/wp-content/uploads/NVM-Express-PCI-Express-Transport-Specification-Revision-1.2-2025.03.11-Ratified-1.pdf) ## Four submission queues, one completion queue and 64 unfinished reads Consider one fictional PCIe SSD and controller. Stipulate a supported, allocated and created arrangement with four I/O SQs sharing one CQ, with adequate resources for the illustrated work. At one instant, each SQ has 16 reads submitted through it for which the host has not received completion. Each read requests 4 KiB. These are invented inputs, not specifications for a product. The outstanding command count is 4 x 16 = 64. The requested transfer quantity is 64 x 4,096 = 262,144 bytes, or 256 KiB. This sums the bytes requested by those reads; it does not establish that all requested addresses are different. The 16 is a stipulated unfinished-command count for each SQ, not a ring size. Some command entries may already have been consumed by the controller. The example supplies neither ring occupancy nor the number of flash operations executing at that instant. The model still contains one SSD. It has not acquired 64 drives, 64 NAND channels or 256 KiB of additional storage capacity. The shared CQ identifies where completion reports arrive; it establishes neither serial execution nor simultaneous media service. If the host subsequently receives eight of these completions, with no new submissions or other command removals, 56 commands remain outstanding. Counting those eight reports without an elapsed interval gives no completion rate. Neither snapshot supplies a 64-fold speed claim or any measured performance result. References: [U1](https://physics.nist.gov/cuu/Units/binary.html) ## More host-side organization can help without adding media resources Linux's blk-mq documentation explains a concrete host-side problem: several processors contending around a single block-I/O queue and lock. Multiple queues can reduce that shared point of contention. Its software staging and hardware dispatch queues belong to the Linux block layer; they should not all be counted as NVMe SQs. NVM Express's historical 2018 architecture explainer also cautions that the queue-to-core affinity shown in its drawing is not compulsory. A diagram placing queues beside CPU cores does not establish a universal one-queue-per-core requirement or an exclusive core allocation. Removing a host-side contention opportunity can help expose capability the device already has. It does not multiply that capability by the number of queues. The offered workload must supply useful work, and the actual controller and media must service it. Extra available queues alone establish no improvement for a workload already limited elsewhere. References: [K1](https://docs.kernel.org/block/blk-mq.html), [E1](https://nvmexpress.org/base-nvm-express-part-one/) ## Compare a supported arrangement with the result you need Suppose Offer A quotes only a theoretical NVMe queue maximum. Offer B identifies the offered controller, applicable firmware and host software, distinguishes supported and allocated SQ/CQ resources, and describes the created associations used for its stated workload. B makes its command organization assessable. A still needs that explanation; its omission does not prove the device lacks the resources. If B also claims a performance advantage, ask what evidence connects the actual arrangement to the required workload. Retain request sizes, read/write mix, offered concurrency, observation interval and completion boundary. Identify whether the submission describes documented capability, a proposed allocation or an observed result. The linked IOPS, throughput and latency article develops that performance comparison. A report showing many created queues but work on only one answers a different question from a report showing work distributed across them. Neither observation, alone, counts physical media channels or demonstrates that all submitted work ran simultaneously. Ask which constraint the claimed arrangement addresses before accepting a numerical speed multiplier. Keep neighboring decisions distinct. The dual-port NVMe guide examines access paths and data copies; the ZNS guide examines permitted write placement. Power-loss protection and atomic-write semantics require their own evidence. A common CQ identity cannot supply an execution-order or durability promise. ## Bring the selected equipment to the physical installation discussion Once the storage and platform owners have selected the equipment, Leviathan's rack-and-stack service can discuss an agreed package of equipment mounting, IT cabling, labels and physical installation records. Use the related service and project-inquiry links with a nonconfidential equipment list, rack positions, released connection requirements and site constraints. Identify the appointed supplier and the owners of host software, storage configuration and workload acceptance. Those decisions define the selected system; the physical inquiry defines the installation work and required handoff. References: [L1](https://www.leviathansystems.co/services/rack-and-stack) ## Primary sources - [N1 — NVM Express Base Specification, Revision 2.2, March 11, 2025](https://nvmexpress.org/wp-content/uploads/NVM-Express-Base-Specification-Revision-2.2-2025.03.11-Ratified-1.pdf). Checked 2026-10-20. The 2025 edition's sections 2.1–2.2, 3.3–3.3.1, 3.3.3.1 and 3.4.5 distinguish queue associations, allocations, slots and outstanding commands. - [P1 — NVMe over PCIe Transport Specification, Revision 1.2, March 11, 2025](https://nvmexpress.org/wp-content/uploads/NVM-Express-PCI-Express-Transport-Specification-Revision-1.2-2025.03.11-Ratified-1.pdf). Checked 2026-10-20. Sections 3.2 and 3.4 distinguish host-addressable queues, shared completion associations, entry consumption and command completion in the PCIe model. - [E1 — NVM Express: Base NVM Express – Part One](https://nvmexpress.org/base-nvm-express-part-one/). Checked 2026-10-20. Historical 2018 architecture explanation: queue-to-core affinity in the illustration is optional. Its historical product-support ranges are not specifications for an offered device. - [K1 — Linux kernel documentation: Multi-Queue Block IO Queueing Mechanism (blk-mq)](https://docs.kernel.org/block/blk-mq.html). Checked 2026-10-20. Background and Operation explain host contention and distinguish software staging from hardware dispatch queues. This Linux example supplies no universal NVMe mapping or tuning prescription. - [U1 — NIST: Prefixes for binary multiples](https://physics.nist.gov/cuu/Units/binary.html). Checked 2026-10-20. Binary prefix definitions support the byte conversion. Queue counts, request quantities and the later completion count are original hypothetical inputs. - [L1 — Leviathan Systems: Rack-and-Stack / Colocation](https://www.leviathansystems.co/services/rack-and-stack). Checked 2026-10-20. The existing service covers agreed equipment mounting, IT cabling, labels and physical installation records; project-specific scope and availability are discussed through its inquiry. ## Related Leviathan resources - [Storage IOPS, throughput and latency](/articles/gpu-storage-iops-throughput-latency-comparison) - [Dual-port NVMe: access paths and data copies](/articles/dual-port-nvme-ssd-paths-versus-data-replicas) - [Zoned NVMe: write placement and zone capacity](/articles/zoned-nvme-ssd-write-contract-and-zone-capacity) - [NVMe atomic writes, persistent completion and transactions](/articles/nvme-atomic-write-versus-persistence-and-transactions) - [Rack-and-stack installation scope](/services/rack-and-stack) - [Discuss the selected equipment's physical installation](/contact?service=rack-and-stack&from=%2Farticles%2Fnvme-submission-completion-queues-versus-media-parallelism) ## Selected equipment needs physical installation? Share the equipment list, released rack and connection plans, site constraints and required physical records to discuss the installation scope and availability. [Discuss the scope](/contact?service=rack-and-stack&from=/articles/nvme-submission-completion-queues-versus-media-parallelism)