--- title: "Chiplets, 2.5D and 3D Packaging: What Is Inside One AI Accelerator?" description: "Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20." canonical: "https://www.leviathansystems.co/articles/gpu-chiplets-2-5d-3d-packaging-system-boundaries" last-updated: "2026-10-20" --- # Chiplets, 2.5D and 3D Packaging: What Is Inside One AI Accelerator? Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20. Chiplets describe how a chip design is divided among dies. The terms 2.5D and 3D describe how dies are integrated, and those arrangements can be combined. Several compute and I/O dies can belong to one accelerator device. Identify the physical level behind each claim before comparing device counts, memory, boards or complete servers. ## Identify the object inside the offer An accelerator announcement can move from silicon to a complete server in a few sentences. Keep the objects separate. A die is an individual piece of semiconductor containing circuitry. A compute die carries processing resources; an I/O die can carry communication and other system functions. A chiplet is a die intended to work with other dies as part of a larger integrated design. Its role matters more than the suggestion that it is merely a smaller GPU. An HBM stack is a memory assembly containing multiple DRAM dies. An interposer provides connections among components within a package. The semiconductor package brings its constituent dies and connections together; an accelerator board or module carries packaged devices and associated circuitry. A server contains accelerator assemblies alongside its other system components. AMD's ROCm 7.2.4 MI300 documentation distinguishes compute dies, I/O dies, HBM stacks and accelerator modules. NVIDIA's DGX H100/H200 introduction separately describes the GPUs within a complete system. These are useful examples of the hierarchy. When a seller says chip, ask whether the quantity refers to a die, a packaged accelerator or a board-level product before carrying it into an equipment comparison. References: [A1](https://rocmdocs.amd.com/en/docs-7.2.4/conceptual/gpu-arch/mi300.html), [A2](https://rocm.blogs.amd.com/software-tools-optimization/compute-memory-modes/README.html), [M1](https://www.micron.com/products/memory/hbm/hbm4), [T1](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm), [N1](https://docs.nvidia.com/dgx/dgxh100-user-guide/introduction-to-dgxh100.html) ## Chiplets divide functions within an integrated device Chiplet describes a design partition, rather than a particular stacking direction. AMD's MI300 documentation identifies the XCD as the die containing GPU computational elements and lower cache levels, while the I/O dies contain system infrastructure. That division explains why adding every logic die together does not produce a meaningful GPU count: some dies perform different supporting functions within the same accelerator. The division also makes communication between dies part of the design. The UCIe Consortium, for example, defines its specification at the interconnect between chiplets within a package. That is a different boundary from an external server connector. A claim about an internal die-to-die link therefore cannot select the cable or adapter required outside the server. Two descriptions can both mention several dies while referring to different architectures. One could count compute chiplets; another could count compute and I/O dies together. Ask for the roles and counting rule before comparing the totals. A larger total alone supplies no ranking of application performance. References: [A1](https://rocmdocs.amd.com/en/docs-7.2.4/conceptual/gpu-arch/mi300.html), [U1](https://www.uciexpress.org/why-choose-us) ## 2.5D connects neighboring components within a package In a 2.5D arrangement, neighboring components communicate through package-level interconnect structures. TSMC's CoWoS family combines logic and HBM stacks. CoWoS-S uses a silicon interposer beneath those components to carry dense connections. The variants matter: CoWoS-R uses an RDL interposer, meaning redistribution layers; CoWoS-L combines RDL with local silicon interconnects. The family name alone does not select one construction. A 2.5D label also does not establish that the accelerator's compute logic is split into chiplets. Identify the logic dies separately from adjacent memory stacks. CoWoS names TSMC's technology family, rather than a universal packaging standard. References: [T1](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm) ## 3D stacking can sit inside a larger 2.5D package 3D integration places dies vertically with electrical connections between them. TSMC's SoIC platform stacks dies with different functions and process technologies. TSMC says the integrated chip can then enter a CoWoS or InFO package: the vertical stack becomes a constituent of a larger assembly. HBM supplies another stacking boundary. Micron's HBM4 explanation describes DRAM dies stacked vertically and connected through silicon by TSVs, or through-silicon vias. The vertical construction inside a memory stack and the arrangement connecting that stack to neighboring logic describe different relationships. A package described as 2.5D can therefore contain stacked components. For a 3D claim, identify the stacked dies and their relationship to the larger package. References: [T2](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm), [M1](https://www.micron.com/products/memory/hbm/hbm4) ## PK-190: count eight devices and 48 logic dies correctly Fictional example PK-190 stipulates one accelerator device per package, with four compute dies and two I/O dies in each package. An offer contains eight such devices. These are invented inputs for explaining quantities, with no mapping to a named GPU. Each package contains six stipulated logic dies. Across the offer, eight times four gives 32 compute dies and eight times two gives 16 I/O dies: 48 logic dies in total. The physical accelerator quantity remains eight. Writing 48 GPUs would replace the offered unit with a mixture of internal components. Writing 48 server tasks would make a further unsupported jump from component population to work scope. Memory stacks need a separate entry. If PK-190's description supplies no stack count, record it as unspecified. The 48 figure excludes memory dies and does not become a total of all semiconductor dies inside the offer. Even a later HBM stack count would need its own stack construction information before anyone could calculate an all-die total. Nor does the example determine a server quantity. Eight devices could belong to a defined server configuration only after the offer identifies that configuration. The useful comparison retains the eight physical accelerator devices, the 32 compute dies and the 16 I/O dies as different quantities. ## Keep physical counts separate from logical devices The runtime view adds another counting rule. AMD's February 9, 2025 MI300 partitioning article explains that its SPX mode presents an MI300X as one logical compute element, while CPX exposes its compute dies as separate logical GPUs. That named example demonstrates why a software device list and a physical equipment list can have different totals without either being an inventory error. For an actual comparison, record physical accelerator quantity and the software-visible allocation separately. Ask the platform owner which supported configuration the workload will use. Neither PK-190's fictional die count nor the words chiplet or 3D establish a logical partition count, concurrent-job entitlement or application result. This distinction is an interpretation aid; it supplies no configuration procedure. References: [A2](https://rocm.blogs.amd.com/software-tools-optimization/compute-memory-modes/README.html) ## Read an announcement at the level its evidence supports Start with the claim's noun and boundary. A compute-die count describes internal partitioning. A stacking statement describes a relationship between dies. A package-family name identifies an integration technology. A board interface belongs to the actual module or card specification, and a cooling arrangement belongs to the configured product that implements it. Moving between those levels requires additional evidence. TSMC's SoIC description allows dies made with different process technologies in one integrated chip. Attribute each node claim to the die it describes; one compute-die label cannot characterize all dies or the package. Use three focused follow-ups when a packaging headline appears in an offer. Ask which functions and memory structures the count includes. Ask which exact accelerator, board and complete system are being offered. Then obtain the evidence for the decision still being made: workload results for application capacity, applicable system documentation for interfaces and service units, and the supplier's own offer for delivery terms. Packaging terminology supplies none of those missing records by itself. In particular, chiplet counts do not identify a replaceable service unit or prove board interchangeability. The relevant product and service documentation must establish those properties. Likewise, a packaging roadmap cannot settle a particular system's lead time, server cooling or site fit. The mechanism can explain the architecture while those purchase questions remain open. References: [T2](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm), [U1](https://www.uciexpress.org/why-choose-us) ## Bring the complete system to installation planning After identifying the accelerator architecture, continue the comparison at the complete system level. The MI300X-versus-H100 guide compares named server options, while the HGX-versus-DGX guide explains platform and delivered-system boundaries. Use those resources for the next decision instead of turning a package diagram into an installation scope. For Leviathan's rack-and-stack service, share the exact supplied equipment models and quantities, delivered assembly state, approved rack positions, mounting requirements and external connection schedule through the project inquiry. Leviathan can discuss agreed equipment mounting, IT cabling, labels and physical handoff records. Semiconductor design and package assembly are outside this service; product-controlled installation, facility power and cooling, and software commissioning need their applicable owners. The service discussion concerns the identified physical system and site requirements. References: [L1](https://www.leviathansystems.co/services/rack-and-stack) ## Primary sources - [T1 — TSMC CoWoS: 2.5D integration and family variants](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm). Checked 2026-10-20. CoWoS family mechanisms and interposer variants. No customer-SKU mapping, geometry, yield, capacity or supply forecast is adopted. - [T2 — TSMC-SoIC: wafer-level 3D stacking and further package integration](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm). Checked 2026-10-20. Stacking, heterogeneous die technologies and incorporation into CoWoS or InFO. No specific accelerator layout or manufacturing recipe is supplied. - [A1 — AMD ROCm 7.2.4: MI300 Series microarchitecture](https://rocmdocs.amd.com/en/docs-7.2.4/conceptual/gpu-arch/mi300.html). Checked 2026-10-20. Versioned MI300 compute/I/O roles and device-to-module hierarchy; page dated February 19, 2026. No benchmark, universal layout or PK-190 product mapping. - [A2 — AMD: Deep dive into the MI300 compute and memory partition modes](https://rocm.blogs.amd.com/software-tools-optimization/compute-memory-modes/README.html). Checked 2026-10-20. February 9, 2025 MI300X example distinguishing physical and logical devices in SPX/CPX. No configuration instructions or measured performance claims are adopted. - [M1 — Micron HBM4: explanation of stacked DRAM and TSV connections](https://www.micron.com/products/memory/hbm/hbm4). Checked 2026-10-20. Physical memory-stack mechanism only. No HBM4 capacity, speed, production status or integration into a named accelerator is inferred. - [U1 — UCIe Consortium: package-level chiplet interconnect scope](https://www.uciexpress.org/why-choose-us). Checked 2026-10-20. The specification's within-package interconnect boundary only; no UCIe implementation, compliance or interoperability is attributed to a named GPU. - [N1 — NVIDIA DGX H100/H200 User Guide: system introduction](https://docs.nvidia.com/dgx/dgxh100-user-guide/introduction-to-dgxh100.html). Checked 2026-10-20. Complete systems contain GPUs and other components. No package layout, site requirements or field procedure is transferred from this system example. - [L1 — Leviathan rack-and-stack installation service](https://www.leviathansystems.co/services/rack-and-stack). Checked 2026-10-20. Agreed physical mounting, IT cabling, labels and handoff scope; semiconductor design or package manufacturing is not represented as a service. ## Related Leviathan resources - [MI300X vs H100: compare the complete server options](/articles/amd-mi300x-vs-nvidia-h100) - [HGX vs DGX: identify the platform and purchased system](/articles/hgx-vs-dgx-deployment) - [GPU memory capacity: distinguish device and system totals](/articles/data-center-gpu-memory-capacity-comparison) - [Rack-and-stack installation scope](/services/rack-and-stack) - [Discuss a physical installation project](/contact?service=rack-and-stack&from=%2Farticles%2Fgpu-chiplets-2-5d-3d-packaging-system-boundaries) ## Discuss installation of the identified system Share the exact equipment, delivered configuration, site location and available rack and connection plans to discuss physical installation scope and availability. [Discuss the scope](/contact?service=rack-and-stack&from=/articles/gpu-chiplets-2-5d-3d-packaging-system-boundaries)