--- title: "Why Move Power Wiring to the Back of a Chip?" description: "Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20." canonical: "https://www.leviathansystems.co/articles/backside-die-power-delivery-versus-signal-interconnect" last-updated: "2026-10-20" --- # Why Move Power Wiring to the Back of a Chip? Leviathan Systems — Technical content Published 2026-10-20; updated 2026-10-20. Backside power delivery moves power distribution to the opposite side of the die from the main signal wiring. Separating the networks can free routing space and provide a less resistive path to the transistors. It explains an internal chip-design improvement; assessing a finished server still requires product and workload evidence. ## Locate the front and back within the die Start with a cross-section of the silicon die. The front side contains the transistors and the overlying metal interconnect stack. In conventional frontside delivery, that stack accommodates both signal connections and power distribution. Intel's June 5, 2023 PowerVia explanation describes moving power wiring to the other side of the transistor layer, leaving frontside routing focused on signals. These names refer to the chip's structure. Packaging can change how the die is oriented in the finished product. Backside power therefore gives no instruction about which face of a circuit board points upward, where a server supply sits or where a cold plate belongs. References: [BP3](https://www.intel.com/content/www/us/en/newsroom/news/powervia-intel-achieves-chipmaking-breakthrough.html) ## Separate two networks competing for routing space Signal interconnect carries information between circuit elements. The power delivery network supplies the active devices and their reference voltage. Imec's November 25, 2022 explanation describes the traditional arrangement in which these networks share the frontside metal stack. Power must reach the devices through wires and vias, the connections between wiring levels. As more circuitry needs connections, power routing consumes space that signal routing also needs. Increasing transistor density alone does not solve that wiring problem. Moving power distribution to the back gives designers another physical region for the supply network and releases frontside routing resources. There is an electrical benefit to pursue as well. Imec's August 28, 2023 discussion explains that backside power conductors can be made larger and less resistive. Their resistance contributes to the voltage lost along the delivery path, commonly called IR drop. The two objectives are connected: allocate space more effectively and deliver power with less resistive drop. Their realized benefit depends on the implementation. References: [BP2](https://www.imec-int.com/en/articles/how-power-chips-backside), [BP4](https://www.imec-int.com/en/articles/backside-power-delivery-options-dtco-study) ## PowerVia and RibbonFET change different things Intel's 18A page, checked October 20, 2026, describes PowerVia relocating coarse-pitch metal layers and connection bumps to the die's back side. Nano-scale through-silicon vias, or nano-TSVs, supply power within each standard cell, a layout unit used to build logic. The same page describes RibbonFET as Intel's gate-all-around transistor architecture: the gate surrounds the channel to control it electrostatically. PowerVia concerns the route supplying the circuitry; RibbonFET concerns control inside the transistor. A gate-all-around label alone does not establish backside power delivery. Likewise, a backside-power label does not identify the gate structure. Imec describes applicability across transistor architectures and multiple backside connection options. Establish each feature from the relevant process description; one vendor's implementation cannot define every process node. References: [BP1](https://www.intel.com/content/www/us/en/foundry/process/18a.html), [BP2](https://www.imec-int.com/en/articles/how-power-chips-backside), [BP4](https://www.imec-int.com/en/articles/backside-power-delivery-options-dtco-study) ## A fictional resistor isolates the delivery-loss mechanism Consider an invented ideal DC example with current fixed at exactly 10 A. Represent just one delivery-path resistance term as 1 mΩ, or 0.001 Ω. The voltage drop is current multiplied by resistance: 10 A × 0.001 Ω = 0.010 V, or 10 mV. Dissipation in that resistor is current squared multiplied by resistance: (10 A)² × 0.001 Ω = 0.1 W. Now stipulate that this one term falls to 0.5 mΩ while the current remains exactly 10 A. The drop becomes 5 mV and the resistor dissipates 0.05 W. The difference is 5 mV of drop and 0.05 W of loss in the stipulated element. This arithmetic explains why resistance matters: less voltage is lost in delivery and less power is dissipated in that element. It assumes no change in current. It supplies no transistor operating voltage, actual chip resistance, switching behavior or transient-droop result. The two resistor values do not represent measured frontside and backside chips. A real design distributes current through many connections, and this calculation isolates only one term. It cannot quantify PowerVia's benefit or be multiplied by a rack's chip count to predict facility savings. ## Die routing and package integration answer different questions A backside power connection describes how power reaches circuitry on a die. A chiplet description identifies a division of functions among dies, while a stacking description identifies how dies are combined. The existing chiplet and packaging guide explains those integration choices. The presence of a through-silicon via does not by itself supply a chiplet count or prove that another compute die has been stacked above it. Identify what the connection joins and what it carries. In the PowerVia description, the nano-TSVs belong to the power delivery mechanism. For example, a description listing gate-all-around transistors, backside power and a multi-die package contains three architectural claims. Evidence for one leaves the other two to be established. Keeping them separate helps a buyer understand which change a performance explanation actually credits. References: [BP1](https://www.intel.com/content/www/us/en/foundry/process/18a.html) ## Assess the finished product with product evidence Lower delivery loss can be valuable without guaranteeing lower server input. A chip designer can pursue performance, denser layouts or efficiency using the available design freedom. The presence of a backside network does not establish which trade-off a particular product makes. If two system offers credit their efficiency to a process feature, compare the completed workload, performance requirement, delivered configurations and measured energy boundary. A mechanism explains a possible contributor; a comparable result establishes what the offered system achieved under the stated conditions. The GPU benchmark guide develops that comparison. Power-control policy is another question. Backside wiring does not identify a requested GPU limit, the effective policy or a complete-server input limit. The companion power-cap article covers those distinctions. Retain the actual system's input requirements and the facility owner's allocation decision when moving into deployment planning; a silicon-routing improvement supplies neither a revised system rating nor additional site capacity. ## Bring the selected system to physical planning Once the architecture comparison leads to a selected system, Leviathan's rack-and-stack service can discuss agreed equipment mounting, IT cabling, labels and physical installation records. Semiconductor design and fabrication are outside that service. Use the related project inquiry to share the exact equipment models and quantities, delivered assembly state, site location, approved rack positions and available connection schedule. Those inputs support a concrete discussion of physical installation scope and availability. ## Primary sources - [BP1 — Intel 18A: PowerVia and RibbonFET mechanism descriptions](https://www.intel.com/content/www/us/en/foundry/process/18a.html). Checked 2026-10-20. Named power-routing and gate-control mechanisms in the current Intel 18A description. - [BP2 — Imec: Backside power delivery](https://www.imec-int.com/en/articles/how-power-chips-backside). Checked 2026-10-20. November 25, 2022 explanation of shared frontside routing and applicability across transistor architectures. - [BP3 — Intel: With PowerVia, Intel Achieves a Chipmaking Breakthrough](https://www.intel.com/content/www/us/en/newsroom/news/powervia-intel-achieves-chipmaking-breakthrough.html). Checked 2026-10-20. June 5, 2023 explanation of die orientation and separation of power and signal wiring. - [BP4 — Imec: Backside power delivery options — a DTCO study](https://www.imec-int.com/en/articles/backside-power-delivery-options-dtco-study). Checked 2026-10-20. August 28, 2023 research discussion of routing, resistive drop and differing backside connection topologies. ## Related Leviathan resources - [Chiplets, 2.5D and 3D packaging: distinguish integration levels](/articles/gpu-chiplets-2-5d-3d-packaging-system-boundaries) - [GPU power caps and complete-server input](/articles/gpu-power-cap-versus-server-input-limit) - [GPU performance and measured system energy](/articles/which-gpu-is-fastest-workload-benchmarks) - [Rack-and-stack installation scope](/services/rack-and-stack) - [Discuss installation of the selected system](/contact?service=rack-and-stack&from=%2Farticles%2Fbackside-die-power-delivery-versus-signal-interconnect) ## Discuss physical installation of the selected system Share the equipment list, site location, rack plans and connection requirements to discuss the physical installation package and availability. [Discuss the scope](/contact?service=rack-and-stack&from=/articles/backside-die-power-delivery-versus-signal-interconnect)